A standard TTL inverting output buffer circuit useful as a line driver, for example in eight bit latched transceivers, is illustrated in FIG. 1. TTL input signals of high and low potential levels received at the input V.sub.IN, propagate through internal nodes of the output buffer circuit and are inverted and transmitted at the output V.sub.OUT. The pullup transistor element is provided by Darlington configuration transistor pair Q12A, Q12B which sources current to the output V.sub.OUT from the high potential level output supply rail V.sub.CCO through Schottky diode D10 for transmitting high potential level output signals V.sub.OH.
The pulldown transistor element is provided by parallel transistors Q13A, Q13B which sink current from the output V.sub.OUT to the low potential level output ground rail GND for transmitting low potential level output signals V.sub.OL. The pullup and pulldown transistor elements are controlled in opposite phase by phase splitter transistor element Q10 having a collector node coupled to the base node BDAR of the Darlington transistor element Q12A and having an emitter node coupled to the base node of the pulldown transistor element Q13A, Q13B.
The phase splitter transistor element Q10 is coupled to the input V.sub.IN through an overdrive and clamp input circuit provided by emitter follower input transistor element Q6 and external clamp diode elements D6A and D6 coupled between the base node of the input emitter follower transistor element Q6 and the collector node of phase splitter transistor element Q10. Q6 provides base drive "overdrive" current for rapid turn on of the phase splitter transistor element Q10. External clamp diodes D6A, D6 clamp the operation of the phase splitter transistor element Q10 out of deep saturation and, for example, in the threshold or soft saturation operation regions for rapid turn off. The collector node of phase splitter Q10 is coupled to the internal high potential level supply rail V.sub.CCI through resistors R10,R19 and the pseudorail circuit provided by emitter follower transistor elements Q18,Q21, controlled by pseudorail bus PRAIL. The input V.sub.IN is similarly coupled to the internal supply rail V.sub.CCI through resistor R23 and the pseudorail circuit. The emitter node of emitter follower input transistor element Q6 is coupled to the low potential power rail GND through a stack of voltage drop component elements R8, D17B.
To accelerate transition from high to low potential level at the output V.sub.OUT, the output buffer circuit incorporates a feedback transistor element Q11 and associated feedback and buffer circuit components elements D19, R12, D11 and R30. The feedback transistor element Q11 is coupled through Schottky diode D19 between the output V.sub.OUT and the collector node of phase splitter transistor element Q10 to accelerate turn off of the pulldown transistor element Q13A, Q13B. The stack of voltage drop components R14, D14 at the emitter node of phase splitter transistor element Q10 provide a squaring network at the base node of the pulldown transistor element Q13A, Q13B.
The output buffer circuit of FIG. 1 is a tristate circuit for holding a high impedance third state at the output V.sub.OUT in response to a high potential level output enable OE signal. OE transistor element QOE and associated circuit components R15C, R15D, D17A, D27, D26, D40, Q14, D15, R33, hold off the Darlington transistor pair Q12A, Q12B, feedback transistor element Q11, phase splitter transistor element Q10, and input transistor element Q6 in response to an OE high potential level signal. A DC Miller killer circuit is provided by DC Miller killer transistor element QDCMK and associated components R15A, R15B which holds off the pulldown transistor element Q13A,Q13B during the tristate.
Other standard features of the circuit of FIG. 1 include an anti-undershoot or undershoot correcting circuit R22,Q22,D30,D31, and an AC Miller killer circuit ACMK.
A disadvantage of the circuit of FIG. 1 is that the high potential level output signal V.sub.OH is referenced to the output supply V.sub.CCO which may vary, for example, as much as 1 volt or more. With the V.sub.OH pulled to a higher potential level, the propagation delay for transition from high to low potential level at the output is increased. Furthermore, because of additional charge stored in the output capacitance, ground bounce noise also increases. In an effort to restore switching speed and reduce ground bounce, a 6V.sub.BE clamp circuit D33-D38 has been coupled between the base node BDAR of the Darlington transistor element Q12A,Q12B and the ground rail GND as illustrated in FIG. 2. This V.sub.OH clamp circuit clamps the high potential output signal V.sub.OH level at a maximum voltage level and also references V.sub.OH to the ground rail GND. A disadvantage of the circuit of FIG. 2 however is that it is temperature sensitive and is effective only at hot temperatures.